Home of the Luna place and route tools
Luna is a robust place and route tool intended for IC processes with features sizes greater than 100nm. We are currently working on a first version and will be releasing the source code under a liberal open source license.
Luna integrates well into the existing ecosystem of open-source EDA tools, such as Yosys and KLayout.
Cell browser
Tech layer setup
Floorplan: generated standard cell rows (blue) with macro blocks (red)
PicoRV32 RISC-V cpu placement (preliminary)
